1. Field of the Invention
The present invention relates generally to memory systems utilized by high-speed data processors and more particularly relates to a memory hierarchy including high-speed data caches.
2. Related Art
Super-computers operating at billions of floating point operations per second (gigaflops) based on microprocessor architectures are entering the marketplace.
Although supercomputers are usually characterized by their impressive floating-point compute speed, memory size and bandwidth also differentiates them from other computers. Each floating point operation (flop) requires between one and three memory accesses per operation. Accordingly, a several hundred megaflop microprocessor requires a memory hierarchy capable of delivering gigabytes per second of bandwidth.
Pipelined memories are available that provide sufficiently high bandwidth. However, it is well-known that the latency associated with these memories directly impacts the execution speed of integer programs such as operating systems and compilers as well as the scaler portion of floating point programs. These programs prefer to access integer and address data directly from a short latency memory device such as a small on-chip cache.
Accordingly, the conflicting demands of integer and floating point operations provide a major challenge to designing microprocessor based supercomputers.